1. Field of Invention
The present invention relates to input/output structure of a silicon chip. More particularly, the present invention relates to a silicon chip design having a mixed input/output slot structure.
2. Description of Related Art
FIG. 1 is a sketch of a silicon chip having a core limited design. As shown in FIG. 1, the silicon chip 1 has a core region 2 and a number of input/output slots (I/O slots) 3 inside the input/output area (I/O area) 4. The I/O area 4 is located on a peripheral strip surrounding the core region 2.
FIG. 2 is a sketch of a silicon chip having a pad limited design. As shown in FIG. 2, the pad limited design has a structure similar to that of the core limited design. The silicon chip 5 also has a core region 6 and a number of input/output slots (I/O slots) 9 inside the input/output area (I/O area) 8. However, there is an additional wiring area 7 between the core region 6 and the input/output area 8.
In general, the core region 2 of silicon chip 1 as shown in FIG. 1 has a high gate count. In other words, the internal circuitry of core region 2 is more complex than that of core region 6. Hence, core region 2 is much bigger than core region 6, as shown in FIG. 2. However, the pin count of the core limited design is generally less than that of the pad limited design. Therefore, the input/output area 4 is able to surround the core region 2 closely without extra wiring area, and the size of the chip is mainly determined by surface area occupied by the core region. If surface area in the core region can be reduced, area for the whole silicon chip can be reduced as well. This is why this type of chip is called a core limited design chip.
In FIG. 2, the silicon chip in the core region 6 generally has a lower gate count because the internal circuitry is simpler. Therefore, the core region 6 is relatively smaller. However, the number of pins it has is larger, and hence there is a wiring region 7 having very few actual wires and lots of blank space, which is a great waste of chip area. In general, this wiring region 7 is regarded as part of the core region, and the input/output slots 9 inside the input/output area 8 directly affect the chip area. Thus, if the width of each input/output slots 9 can somehow be reduced, for example, by producing a narrow and long input/output slot, the chip area can be reduced while more pins can be accommodated as well. This type of chip design is commonly known as a pad limited design chip.
FIG. 3 shows the shape of one of the input/output slots in the input/output area of FIG. 1. FIG. 4 shows the shape of one of the input/output slots in the input/output area of FIG. 2. As shown in FIG. 3, the input/output slot 3 is generally designed to have wide and fat dimensions so that chip area can be saved. The input/output slot 3 has a driver 10 and a bonding pad 11. Furthermore, the driver 10 and the bonding pad 11 can be configured into two types, namely A type and B type. That is, the bonding pad 11 can be within the driver 10, or the bonding pad 11 and the driver 10 can be separated from each other. The input/output slot design 9 as shown in FIG. 4 is normally used in a pad-limited design. It has a narrow and long profile so that chip area can be saved. Similarly, the input/output slot 9 has a driver 12 and a bonding pad 13, and has two types of combination, namely A type and B type.
FIG. 5 illustrates the design rules of input/output slots under the same group. Because input/output slots on all four sides may require interconnection, the design of input/output slots must facilitate interconnection. Therefore, input/output slots that need to be interconnected are grouped together and have similar design. As shown in FIG. 5, the input/output slots 14 and 15 both have the same height, but the width is different. Since the width of input/output slots 14 and 15 are different, each slot can accommodate different current ratings.
FIG. 6 is a diagram showing conventional layout of input/output slots around the silicon chip. As shown in FIG. 6, the input/output slots along side 16 need to accommodate a large current, and therefore requires larger drivers. Hence, the width of the input/output slots is larger. On the other hand, the input/output slots along side 18 need to accommodate only a small current, and therefore require smaller drivers. Hence, the width of the input/output slots is smaller. In FIG. 6, interconnecting devices between input/output slots 18 are not shown because no input/output slots are present for the interconnecting device to act. Due to the difference in current flowing from the input/output slots on each side of the chip, chip size is affected by the width of I/O slots on a particular side. Hence, the remaining sides of the silicon chip are under-utilized and optimal use of the chip area will be difficult to realize.
In light of the foregoing, there is a need to provide a method for better utilizing the chip area.